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9.2.2   FDD specific parameters   PDF-p. 670
9.2.2.a2   ACK-NACK Repetition Factor [R5]
9.2.2.b2   ACK Power Offset [R5]
9.2.2.A   Active Pattern Sequence Information
9.2.2.B   Adjustment Period   PDF-p. 671
9.2.2.C   Adjustment Ratio
9.2.2.D   AICH Power
9.2.2.1   AICH Transmission Timing      Up
9.2.2.1A   AP Preamble Signature
9.2.2.1B   AP Sub Channel Number
9.2.2.1Ba   Best Cell Portions [R5]   PDF-p. 672
9.2.2.1Bb   Bundling Mode Indicator [R6]
9.2.2.1C   CD Sub Channel Numbers
9.2.2.1Ca   Cell Portion ID [R5]
9.2.2.1D   Channel Assignment Indication
9.2.2.2   Chip Offset
9.2.2.2A   Closed Loop Timing Adjustment Mode
9.2.2.3   Common Channels Capacity Consumption Law   PDF-p. 673      Up
9.2.2.3A   Compressed Mode Deactivation Flag
9.2.2.4   Compressed Mode Method
9.2.2.4A   CPCH Allowed Total Rate
9.2.2.4B   CPCH Scrambling Code Number
9.2.2.4C   CPCH UL DPCCH Slot Format
9.2.2.4Ca   CQI Power Offset [R5]
9.2.2.4Cb   CQI Repetition Factor [R5]
9.2.2.4D   DCH FDD Information   PDF-p. 674
9.2.2.4E   DCHs FDD To Modify
9.2.2.4F   DCH Indicator For E-DCH-HSDPA Operation [R6]   PDF-p. 675      Up
9.2.2.4G   Transport Bearer Not Requested Indicator [R7]
9.2.2.4H   Transport Bearer Not Setup Indicator [R7]
9.2.2.5   D-Field Length
9.2.2.6   Dedicated Channels Capacity Consumption Law
9.2.2.7   Diversity Control Field
9.2.2.8   Diversity Indication
9.2.2.9   Diversity Mode   PDF-p. 676
9.2.2.10   DL DPCH Slot Format
9.2.2.10A   DL DPCH Timing Adjustment [R5]
9.2.2.11   DL frame type      Up
9.2.2.12   DL or Global Capacity Credit
9.2.2.12A   DL_power_averaging_window_size
9.2.2.12B   DL Power Balancing Information [R5]
9.2.2.12C   DL Power Balancing Activation Indicator [R5]   PDF-p. 677
9.2.2.12D   DL Power Balancing Updated Indicator [R5]
9.2.2.13   DL Scrambling Code
9.2.2.13A   DL TPC Pattern 01 Count   PDF-p. 678
9.2.2.13B   DSCH FDD Information
9.2.2.13C   DPC Mode [R4]
9.2.2.13D   DSCH FDD Common Information [R4]      Up
9.2.2.13Da2   E-DCH FDD Information [R6]
9.2.2.13DA   E-DCH FDD Update Information [R6]   PDF-p. 679
9.2.2.13Db   E-DCH FDD Information Response [R6]   PDF-p. 680
9.2.2.13Dc   E-DCH FDD DL Control Channel Information [R6]
9.2.2.13De   E-DCH RL Indication [R6]   PDF-p. 682
9.2.2.13Df   E-DCH FDD Information to Modify [R6]
9.2.2.13Dh   E-DCH Transport Format Combination Set Information (E-TFCS Information) [R6]   PDF-p. 685
9.2.2.13Di   E-TTI [R6]   PDF-p. 686
9.2.2.13Dj   E-DPCCH Power Offset [R6]
9.2.2.13Dk   E-DCH HARQ Power Offset FDD [R6]      Up
9.2.2.13Dl   E-DCH MAC-d Flow Multiplexing List [R6]
9.2.2.13Dm   Maximum Number of Bits per MAC-e PDU for Non-scheduled Transmission [R6]
9.2.2.13Dn   HARQ Process Allocation For 2ms TTI [R6]
9.2.2.13Dp   Reference E-TFCI Power Offset [R6]   PDF-p. 687
9.2.2.13Dq   Extended Reference E-TFCI Power Offset [R7]
9.2.2.13Dr   Extended Maximum Number of Bits per MAC-e PDU for Non-scheduled Transmission [R7]
9.2.2.13E   Enhanced DSCH PC [R4]
9.2.2.13F   Enhanced DSCH PC Counter [R4]
9.2.2.13G   Enhanced DSCH PC Indicator [R4]   PDF-p. 688
9.2.2.13H   Enhanced DSCH PC Wnd [R4]      Up
9.2.2.13I   Enhanced DSCH Power Offset [R4]
9.2.2.13Ia   E- RGCH/E-HICH FDD Code Information [R6]
9.2.2.13Ib   E- AGCH FDD Code Information [R6]
9.2.2.13Ic   E-RGCH Release Indicator [R6]
9.2.2.13Id   E-AGCH Power Offset [R6]   PDF-p. 689
9.2.2.13Ie   E-RGCH Power Offset [R6]
9.2.2.13If   E-HICH Power Offset [R6]
9.2.2.13Ig   E-RGCH 2-Index-Step Threshold [R6]
9.2.2.13Ih   E-RGCH 3-Index-Step Threshold [R6]
9.2.2.13J   E-DCH Capability [R6]   PDF-p. 690      Up
9.2.2.13Ja   E-DCH Capacity Consumption Law [R6]
9.2.2.13K   E-DCH Logical Channel Information [R6]   PDF-p. 691
9.2.2.13L   E-DCH Logical Channel To Modify [R6]
9.2.2.13M   E-DCH MAC-d Flows Information [R6]
9.2.2.13N   E-DCH MAC-d Flows To Delete [R6]   PDF-p. 693
9.2.2.13O   E-DCH MAC-d Flow ID [R6]
9.2.2.13P   E-RNTI [R6]
9.2.2.13Q   E-DCH DDI Value [R6]
9.2.2.13R   E-DCH Provided Bit Rate Value [R6]
9.2.2.13S   E-DCH Provided Bit Rate Value Information [R6]      Up
9.2.2.13T   E-DCH Maximum Bitrate [R6]
9.2.2.13U   E-DCH Processing Overload Level [R6]
9.2.2.13V   E-DCH TTI2ms Capability [R6]
9.2.2.13W   E-DCH SF Capability [R6]   PDF-p. 694
9.2.2.13X   E-DCH HARQ Combining Capability [R6]
9.2.2.13Y   E-DCH Reference Power Offset [R6]
9.2.2.13Z   E-DCH Power Offset for Scheduling Info [R7]
9.2.2.14   FDD DL Channelisation Code Number
9.2.2.14A   FDD DL Code Information   PDF-p. 695
9.2.2.14B   FDD S-CCPCH Frame Offset [R6]      Up
9.2.2.15   FDD SCCPCH Offset
9.2.2.16   FDD TPC DL Step Size
9.2.2.16a2   F-DPCH Capability [R6]   PDF-p. 696
9.2.2.16A   First RLS Indicator
9.2.2.17   Gap Period
9.2.2.18   Gap Position Mode
9.2.2.18a2   HARQ Preamble Mode [R6]
9.2.2.18b2   HARQ Preamble Mode Activation Indicator [R6]
9.2.2.18ba   HARQ Info for E-DCH [R6]
9.2.2.18c2   Logical channel ID [R6]   PDF-p. 697      Up
9.2.2.18A   Limited Power Increase
9.2.2.18B   Inner Loop DL PC Status
9.2.2.18C   IPDL FDD Parameters [R4]
9.2.2.18Ca   HS-DSCH configured indicator [R6]
9.2.2.18D   HS-DSCH FDD Information [R5]   PDF-p. 698
9.2.2.18Da   HS-DSCH FDD Secondary Serving Information [R8]   PDF-p. 700
9.2.2.18E   HS-DSCH FDD Information Response [R5]   PDF-p. 702
9.2.2.18EA   HS-DSCH FDD Secondary Serving Information Response [R8]   PDF-p. 703
9.2.2.18EB   HS-DSCH FDD Secondary Serving Information To Modify [R8]
9.2.2.18EC   HS-DSCH FDD Secondary Serving Information To Modify Unsynchronised [R8]   PDF-p. 705      Up
9.2.2.18Ea2   HS-DSCH FDD Update Information [R5]   PDF-p. 706
9.2.2.18Eaa   HS-DSCH FDD Secondary Serving Update Information [R8]   PDF-p. 707
9.2.2.18Eb2   HS-DSCH Serving Cell Change Information [R6]
9.2.2.18Ec2   HS-DSCH Serving Cell Change Information Response [R6]   PDF-p. 708
9.2.2.18Eca   HS-DSCH Secondary Serving Cell Change Information Response [R8]
9.2.2.18Ed   E-DCH Serving Cell Change Information Response [R6]
9.2.2.18Ee   HS-DSCH TB Size Table Indicator [R7]   PDF-p. 709
9.2.2.18F   HS-PDSCH FDD Code Information [R5]
9.2.2.18G   HS-SCCH FDD Code Information [R5]
9.2.2.18H   HS-SCCH ID [R5]   PDF-p. 710      Up
9.2.2.18I   HS-SCCH Power Offset [R5]
9.2.2.18K   Initial DL DPCH Timing Adjustment Allowed [R6]
9.2.2.19   Max Adjustment Period
9.2.2.20   Max Adjustment Step
9.2.2.20A   Max Number Of PCPCHs   PDF-p. 711
9.2.2.20B   Max Number Of UL E-DPDCHs [R6]
9.2.2.20C   Maximum Set of E-DPDCHs [R6]
9.2.2.20D   Maximum Number Of Retransmissions For E-DCH [R6]
9.2.2.20E   MAC-es Guaranteed Bit Rate [R6]
9.2.2.20F   MAC-e Reset Indicator [R6]      Up

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