Tech-invite   World Map
3GPPspecs     Glossaries     T+       IETF     RFCs     Groups     SIP     ABNFs


Here        Top        Up        Prev        Next
1…      8.3…       9…       9.2                                                 9.3…     




9.2.2   FDD specific parameters   PDF-p. 670
9.2.2.a2   ACK-NACK Repetition Factor [R5]
9.2.2.b2   ACK Power Offset [R5]
9.2.2.A   Active Pattern Sequence Information
9.2.2.B   Adjustment Period   PDF-p. 671
9.2.2.C   Adjustment Ratio
9.2.2.D   AICH Power   AICH Transmission Timing      Up   AP Preamble Signature   AP Sub Channel Number   Best Cell Portions [R5]   PDF-p. 672   Bundling Mode Indicator [R6]   CD Sub Channel Numbers   Cell Portion ID [R5]   Channel Assignment Indication   Chip Offset   Closed Loop Timing Adjustment Mode   Common Channels Capacity Consumption Law   PDF-p. 673      Up   Compressed Mode Deactivation Flag   Compressed Mode Method   CPCH Allowed Total Rate   CPCH Scrambling Code Number   CPCH UL DPCCH Slot Format   CQI Power Offset [R5]   CQI Repetition Factor [R5]   DCH FDD Information   PDF-p. 674   DCHs FDD To Modify   DCH Indicator For E-DCH-HSDPA Operation [R6]   PDF-p. 675      Up   Transport Bearer Not Requested Indicator [R7]   Transport Bearer Not Setup Indicator [R7]   D-Field Length   Dedicated Channels Capacity Consumption Law   Diversity Control Field   Diversity Indication   Diversity Mode   PDF-p. 676   DL DPCH Slot Format   DL DPCH Timing Adjustment [R5]   DL frame type      Up   DL or Global Capacity Credit   DL_power_averaging_window_size   DL Power Balancing Information [R5]   DL Power Balancing Activation Indicator [R5]   PDF-p. 677   DL Power Balancing Updated Indicator [R5]   DL Scrambling Code   DL TPC Pattern 01 Count   PDF-p. 678   DSCH FDD Information   DPC Mode [R4]   DSCH FDD Common Information [R4]      Up   E-DCH FDD Information [R6]   E-DCH FDD Update Information [R6]   PDF-p. 679   E-DCH FDD Information Response [R6]   PDF-p. 680   E-DCH FDD DL Control Channel Information [R6]   E-DCH RL Indication [R6]   PDF-p. 682   E-DCH FDD Information to Modify [R6]   E-DCH Transport Format Combination Set Information (E-TFCS Information) [R6]   PDF-p. 685   E-TTI [R6]   PDF-p. 686   E-DPCCH Power Offset [R6]   E-DCH HARQ Power Offset FDD [R6]      Up   E-DCH MAC-d Flow Multiplexing List [R6]   Maximum Number of Bits per MAC-e PDU for Non-scheduled Transmission [R6]   HARQ Process Allocation For 2ms TTI [R6]   Reference E-TFCI Power Offset [R6]   PDF-p. 687   Extended Reference E-TFCI Power Offset [R7]   Extended Maximum Number of Bits per MAC-e PDU for Non-scheduled Transmission [R7]   Enhanced DSCH PC [R4]   Enhanced DSCH PC Counter [R4]   Enhanced DSCH PC Indicator [R4]   PDF-p. 688   Enhanced DSCH PC Wnd [R4]      Up   Enhanced DSCH Power Offset [R4]   E- RGCH/E-HICH FDD Code Information [R6]   E- AGCH FDD Code Information [R6]   E-RGCH Release Indicator [R6]   E-AGCH Power Offset [R6]   PDF-p. 689   E-RGCH Power Offset [R6]   E-HICH Power Offset [R6]   E-RGCH 2-Index-Step Threshold [R6]   E-RGCH 3-Index-Step Threshold [R6]   E-DCH Capability [R6]   PDF-p. 690      Up   E-DCH Capacity Consumption Law [R6]   E-DCH Logical Channel Information [R6]   PDF-p. 691   E-DCH Logical Channel To Modify [R6]   E-DCH MAC-d Flows Information [R6]   E-DCH MAC-d Flows To Delete [R6]   PDF-p. 693   E-DCH MAC-d Flow ID [R6]   E-RNTI [R6]   E-DCH DDI Value [R6]   E-DCH Provided Bit Rate Value [R6]   E-DCH Provided Bit Rate Value Information [R6]      Up   E-DCH Maximum Bitrate [R6]   E-DCH Processing Overload Level [R6]   E-DCH TTI2ms Capability [R6]   E-DCH SF Capability [R6]   PDF-p. 694   E-DCH HARQ Combining Capability [R6]   E-DCH Reference Power Offset [R6]   E-DCH Power Offset for Scheduling Info [R7]   FDD DL Channelisation Code Number   FDD DL Code Information   PDF-p. 695   FDD S-CCPCH Frame Offset [R6]      Up   FDD SCCPCH Offset   FDD TPC DL Step Size   F-DPCH Capability [R6]   PDF-p. 696   First RLS Indicator   Gap Period   Gap Position Mode   HARQ Preamble Mode [R6]   HARQ Preamble Mode Activation Indicator [R6]   HARQ Info for E-DCH [R6]   Logical channel ID [R6]   PDF-p. 697      Up   Limited Power Increase   Inner Loop DL PC Status   IPDL FDD Parameters [R4]   HS-DSCH configured indicator [R6]   HS-DSCH FDD Information [R5]   PDF-p. 698   HS-DSCH FDD Secondary Serving Information [R8]   PDF-p. 700   HS-DSCH FDD Information Response [R5]   PDF-p. 702   HS-DSCH FDD Secondary Serving Information Response [R8]   PDF-p. 703   HS-DSCH FDD Secondary Serving Information To Modify [R8]   HS-DSCH FDD Secondary Serving Information To Modify Unsynchronised [R8]   PDF-p. 705      Up   HS-DSCH FDD Update Information [R5]   PDF-p. 706   HS-DSCH FDD Secondary Serving Update Information [R8]   PDF-p. 707   HS-DSCH Serving Cell Change Information [R6]   HS-DSCH Serving Cell Change Information Response [R6]   PDF-p. 708   HS-DSCH Secondary Serving Cell Change Information Response [R8]   E-DCH Serving Cell Change Information Response [R6]   HS-DSCH TB Size Table Indicator [R7]   PDF-p. 709   HS-PDSCH FDD Code Information [R5]   HS-SCCH FDD Code Information [R5]   HS-SCCH ID [R5]   PDF-p. 710      Up   HS-SCCH Power Offset [R5]   Initial DL DPCH Timing Adjustment Allowed [R6]   Max Adjustment Period   Max Adjustment Step   Max Number Of PCPCHs   PDF-p. 711   Max Number Of UL E-DPDCHs [R6]   Maximum Set of E-DPDCHs [R6]   Maximum Number Of Retransmissions For E-DCH [R6]   MAC-es Guaranteed Bit Rate [R6]   MAC-e Reset Indicator [R6]      Up

Up        Top        ToC