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TR 25.895 (RAN6)
Analysis of higher chip rates for UTRA TDD evolution

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(W-zip) V6.0.0    2004/09    191 p.

Rapporteur:  Dr. Beale, Martin
See also:  –

This TR contains results of an analysis of the feasibility and potential benefits of higher chip rate UTRA TDD.

The analysis in this document is based on a reference configuration at the reference chip rate of 7.68Mcps. The comparison of this reference system with current UTRA TDD releases allows conclusions to be drawn as to the potential benefits and feasibility of even higher chip rates for UTRA TDD.

The document presents results of an analysis of the reference configuration using channel models appropriate to a higher chip rate system. Link level and system level results are presented. A link budget shows the coverage that can be expected at a higher chip rate. Aspects of UE and UTRAN complexity are considered.

The feasibility of higher chip rate UTRA TDD systems is considered. This document covers aspects such as coexistence, backward compatibility, use in diverse spectrum arrangements and allocations, mobility, application to 3GPP system and services, antenna systems and impacts on signalling, specifications and RAN working groups.

The study of higher chip rate UTRA TDD is based on the assumption that the higher layer protocol architecture for higher chip rate UTRA TDD is unchanged from 3GPP Release 5. It is assumed that higher chip rate UTRA TDD shall be evolved from 3.84Mcps TDD and that the higher chip rate UTRA TDD carrier may exist without the need for a supporting 3.84Mcps TDD carrier.


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1   Scope   Word-p. 8
2   References
3   Definitions, symbols and abbreviations   Word-p. 9
4   Reference Higher Chip Rate Configuration
5   Analysis
5.1   Reference Channel Models      Up
5.2   Link Level Results
5.3   System Level Results   Word-p. 62
5.4   Link Budget   Word-p. 144
5.5   Complexity Analysis   Word-p. 147

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