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TS 25.202 (RAN6)
UTRA – 7.68 Mcps Time Division Duplex (TDD) option –
Overall description –
Stage 2

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(P) V14.0.0    2017/03    32 p.
(P) V13.0.0    2016/01    32 p.
(P) V12.0.0    2014/09    32 p.
(P) V11.0.0    2012/09    32 p.
(P) V10.0.0    2011/03    32 p.
(P) V9.0.0    2009/12    32 p.
(P) V8.0.0    2008/03    32 p.
(P) V7.1.0    2006/10    32 p.

Rapporteur:  Dr. Beale, Martin
See also:  TR 25.895    

This TS is the overall specification for the support of the 7.68Mcps TDD option in UTRA.

The 7.68Mcps TDD option is an evolution of the 3.84Mcps TDD option to a higher chip rate. There exists a great degree of commonality between the 3.84Mcps TDD option and the 7.68Mcps TDD option. Nevertheless, there are many aspects of the 7.68Mcps TDD option that require separate specification to the 3.84Mcps TDD option.


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