Figure 4.2.1-1 | Overview model of the RLC sub layer |
Figure 4.2.1.1.1-1 | Model of two transparent mode peer entities |
Figure 4.2.1.2.1-1 | Model of two unacknowledged mode peer entities |
Figure 4.2.1.3.1-1 | Model of an acknowledged mode entity |
Figure 6.2.2.2-1 | TMD PDU |
Figure 6.2.2.3-1 | UMD PDU containing a complete RLC SDU |
Figure 6.2.2.3-2 | UMD PDU with 6 bit SN (No SO) |
Figure 6.2.2.3-3 | UMD PDU with 12 bit SN (No SO) |
Figure 6.2.2.3-4 | UMD PDU with 6 bit SN and with SO |
Figure 6.2.2.3-5 | UMD PDU with 12 bit SN and with SO |
Figure 6.2.2.4-1 | AMD PDU with 12 bit SN (No SO) |
Figure 6.2.2.4-2 | AMD PDU with 18 bit SN (No SO) |
Figure 6.2.2.4-3 | AMD PDU with 12 bit SN with SO |
Figure 6.2.2.4-4 | AMD PDU with 18 bit SN with SO |
Figure 6.2.2.5-1 | STATUS PDU with 12 bit SN |
Figure 6.2.2.5-2 | STATUS PDU with 18 bit SN |
Table 6.2.3.4-1 | SI field interpretation |
Table 6.2.3.6-1 | D/C field interpretation |
Table 6.2.3.7-1 | P field interpretation |
Table 6.2.3.9-1 | CPT field interpretation |
Table 6.2.3.11-1 | E1 field interpretation |
Table 6.2.3.13-1 | E2 field interpretation |
Table 6.2.3.16-1 | E3 field interpretation |