tech-invite   World Map     

IETF     RFCs     Groups     SIP     ABNFs    |    3GPP     Specs     Glossaries     Architecture     IMS     UICC    |    search     info

Top          in Index          Prev          Next

TS 102 694-2 (ETSI SCP)
Smart Cards –
Test specification for the Single Wire Protocol (SWP) interface –
Part 2:  UICC features

|   ToC   |   ETSI-search   |

(P) V10.3.0    2015-03    118 p.
(P) V9.4.0    2013-07    119 p.
(P) V8.0.0    2011-09    115 p.
(P) V7.4.0    2013-06    110 p.


The present document defines test cases for the UICC relating to Single Wire Protocol (SWP). SWP is the communication interface between the UICC and a contactless frontend (CLF) as specified in TS 102 613.

The aim of the present document is to ensure interoperability between the terminal and the UICC independently of the respective manufacturer, card issuer or operator.

The present document covers the minimum characteristics which are considered necessary for the UICC in order to provide compliance to TS 102 613.

The present document specifies the test cases for:
  • the physical layer of the interface CLF - UICC;
  • the electrical interface of the CLF;
  • the initial communication establishment CLF - UICC;
  • the data link layer.


1   Scope   p. 12
2   References
3   Definitions, symbols and abbreviations
4   Test environment   p. 16
5   Test cases
5.1   Principle of the Single Wire Protocol
5.2   System architecture
5.2.1   General overview
5.2.2   ETSI TS 102 221 support
5.2.3   Configurations   p. 28
5.2.4   Interaction with other interfaces   p. 30
5.3   Physical characteristics   p. 34      Up
5.3.1   Temperature range for card operations
5.3.2   Contacts
5.3.2.1   Provision of contacts
5.3.2.2   Contact activation and deactivation
5.3.2.3   Interface activation
5.3.2.4   Behaviour of a UICC in a terminal not supporting SWP   p. 41      Up
5.3.2.5   Behaviour of a terminal connected to a UICC not supporting SWP   p. 42
5.3.2.6   Inactive contacts
5.4   Electrical characteristics
5.5   Physical transmission layer   p. 50      Up
5.5.1   S1 Bit coding and sampling time
5.5.2   S2 switching management      Up
5.5.3   SWP interface states management   p. 55
5.5.4   Power mode states/transitions and Power saving mode
5.5.4.1   Conformance requirements
5.5.4.2   Test case 1: power states in low power mode (ACT_POWER_MODE)   p. 57
5.5.4.3   Test case 2: power states in low power mode (non-ACT)   p. 58      Up
5.5.4.4   Test case 3: power states in full power mode, without ETSI TS 102 221
5.5.4.5   Test case 4: power saving mode with ETSI TS 102 221 interface - restart ETSI TS 102 221 interface first
5.5.4.6   Test case 5: power saving mode with ETSI TS 102 221 interface - restart ETSI TS 102 613 interface first      Up
5.5.4.7   Test case 6: power saving mode with ETSI TS 102 600 interface - restart ETSI TS 102 600 interface first
5.5.4.8   Test case 7: power saving mode with ETSI TS 102 600 interface - restart ETSI TS 102 613 interface first
5.5.4.9   Void
5.5.4.10   Test case 9: power saving mode in SUSPENDED, with ETSI TS 102 221 interface restarted first      Up
5.5.4.11   Test case 10: power saving mode in SUSPENDED, with ETSI TS 102 221 interface restarted after ETSI TS 102 613 interface   p. 62
5.6   Data link layer
5.6.1   Overview
5.6.2   Medium Access Control (MAC) layer      Up
5.6.3   Supported LLC layers
5.6.4   ACT LLC definition   p. 72      Up
5.7   SHDLC LLC definition      Up
5.7.1   SHDLC overview
5.7.2   Endpoints
5.7.3   SHDLC frames types
5.7.4   Control Field   p. 77
5.7.5   Changing sliding window size and endpoint capabilities
5.7.6   SHDLC context   p. 78
5.7.7   SHDLC sequence of frames      Up
5.7.7.1   Conformance requirements
5.7.7.2   Nomenclature   p. 80
5.7.7.3   Link establishment with default sliding window size
5.7.7.4   Link establishment with custom sliding window size   p. 86      Up
5.7.7.5   Data flow
5.7.7.6   Reject (go N back)
5.7.7.7   Last Frame Loss      Up
5.7.7.8   Receive and not ready
5.7.7.9   Selective reject   p. 93
5.7.8   Implementation      Up
5.8   CLT LLC definition
5.9   Timing and performance
A   State diagrams   p. 103
B   Bibliography   p. 114
C   Core specification version information   p. 115      Up
D   Change history   p. 116

Top