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9.2.2   FDD Specific Parameters   PDF-p. 578
9.2.2.x   ACK-NACK Repetition Factor [R5]      Up
9.2.2.y   ACK Power Offset [R5]
9.2.2.A   Active Pattern Sequence Information
9.2.2.B   Adjustment Period   PDF-p. 579
9.2.2.C   Adjustment Ratio
9.2.2.Ca   Bundling Mode Indicator [R6]   PDF-p. 580
9.2.2.D   Cell Capability Container FDD [R5]
9.2.2.E   Cell Portion ID [R6]   PDF-p. 583   Chip Offset   Closed Loop Mode1 Support Indicator   PDF-p. 584   Closed Loop Mode2 Support Indicator      Up   Closed Loop Timing Adjustment Mode   Compressed Mode Method   DCH FDD Information   E-DCH FDD Information [R6]   PDF-p. 585   E-DCH FDD Information Response [R6]   PDF-p. 586   E-DCH FDD DL Control Channel Information [R6]   PDF-p. 587   E-DCH RL Indication [R6]   PDF-p. 589   E-DCH FDD Information To Modify [R6]   E-DCH Transport Format Combination Set Information (E-TFCS Information) [R6]   PDF-p. 593   E-TTI [R6]   PDF-p. 595      Up   E-DPCCH Power Offset [R6]   Void   E-DCH HARQ Power Offset FDD [R6]   Void   Void   Void   E-DCH MAC-d Flows Information [R6]   Void   Void   Void   E-DCH Maximum Bitrate [R6]   PDF-p. 597   Void   E-DCH Reference Power Offset [R6]   Void   Maximum Number of Bits per MAC-e PDU for Non-scheduled Transmission [R6]   PDF-p. 598   HARQ Process Allocation For 2ms TTI [R6]   Reference E-TFCI Power Offset [R6]   Extended Reference E-TFCI Power Offset [R7]   Extended Maximum Number of Bits per MAC-e PDU for Non-scheduled Transmission [R7]   PDF-p. 599      Up   Transport Bearer Not Requested Indicator [R7]   Transport Bearer Not Setup Indicator [R7]   D-Field Length   Diversity Control Field   Diversity Indication   Diversity Mode   DL DPCH Slot Format   PDF-p. 600   DL DPCH Timing Adjustment [R5]   DL Power   DL Power Balancing Information [R5]      Up   DL Power Balancing Activation Indicator [R5]   PDF-p. 601   DL Reference Power Information [R5]   DL Power Balancing Updated Indicator [R5]   PDF-p. 602   DL Scrambling Code   Downlink Frame Type   DPC Mode [R4]   DRAC Control   DSCH FDD Information   PDF-p. 603   DSCH FDD Information Response   DSCH-RNTI      Up   FDD DCHs To Modify   Enhanced DSCH PC [R4]   Enhanced DSCH PC Counter [R4]   Enhanced DSCH PC Indicator [R4]   Enhanced DSCH PC Wnd [R4]   Enhanced DSCH Power Offset [R4]   PDF-p. 604   Enhanced Primary CPICH Ec/No [R5]   FDD DL Channelisation Code Number   FDD DL Code Information   FDD S-CCPCH Offset      Up   FDD TPC Downlink Step Size   First RLS Indicator   PDF-p. 605   Gap Position Mode   Gap Period (TGP)   Gap Starting Slot Number (SN)   HS-DSCH FDD Information [R5]   HS-DSCH FDD Secondary Serving Information [R8]   PDF-p. 607   HS-DSCH FDD Information Response [R5]   PDF-p. 609   HS-DSCH FDD Secondary Serving Information Response [R8]   PDF-p. 610   HS-DSCH FDD Secondary Serving Information To Modify [R8]   PDF-p. 611      Up   HS-DSCH FDD Secondary Serving Information To Modify Unsynchronised [R8]   PDF-p. 613   HS-DSCH FDD Update Information [R5]   PDF-p. 615   HS-DSCH FDD Secondary Serving Update Information [R8]   PDF-p. 616   HS-DSCH Configured Indicator [R6]   HS-SCCH Power Offset [R7]   PDF-p. 617   E-DCH FDD Update Information [R6]   HS-DSCH Serving Cell Change Information [R6]   HS-DSCH Serving Cell Change Information Response [R6]   PDF-p. 618   HS-DSCH Secondary Serving Cell Change Information Response [R8]   HS-DSCH TB Size Table Indicator [R7]      Up   E-DCH Serving Cell Change Information Response [R6]   PDF-p. 619   IB_SG_POS   IB_SG_REP   Inner Loop DL PC Status   Initial DL DPCH Timing Adjustment Allowed [R6]   Limited Power Increase   IPDL FDD Parameters   PDF-p. 620   Length of TFCI2 [R4]   Void   Void   Void   Max Adjustment Period   Max Adjustment Step      Up   Max Number of UL DPDCHs   CQI Feedback Cycle k [R5]   PDF-p. 621   CQI Power Offset [R5]   CQI Repetition Factor [R5]   Measurement Power Offset [R5]   Maximum Set of E-DPDCHs [R6]   Void   Min DL Channelisation Code Length [R10]   PDF-p. 622   Min UL Channelisation Code Length   Multiplexing Position   NACK Power Offset [R5]      Up   Number of DL Channelisation Codes   Pattern Duration (PD)   PDF-p. 623   PC Preamble   PDSCH Code Mapping   Phase Reference Update Indicator [R5]   Power Adjustment Type   Power Control Mode (PCM)   Power Offset   Power Resume Mode (PRM)   Preamble Signatures   PDF-p. 624      Up   Primary CPICH Ec/No   Primary CPICH Usage For Channel Estimation [R5]   Propagation Delay (PD)   Extended Propagation Delay [R7]   PRACH Minimum Spreading Factor   QE-Selector   PDF-p. 625   Qth Parameter [R5]   RACH Sub Channel Numbers   RL Set ID   RL Specific E-DCH Information [R6]      Up   Received Total Wide Band Power   S-Field Length   PDF-p. 626   Void   Scrambling Code Change   Scrambling Code Number   Secondary CCPCH Info   Secondary CCPCH Slot Format   Secondary CPICH Information [R5]   Secondary CPICH Information Change [R5]   Serving E-DCH RL [R6]   Slot Number (SN)   PDF-p. 627      Up   Split Type   SRB Delay

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