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9.2.2   FDD Specific Parameters
9.2.2.x   ACK-NACK Repetition Factor [R5]
9.2.2.y   ACK Power Offset [R5]      Up
9.2.2.A   Active Pattern Sequence Information
9.2.2.B   Adjustment Period   PDF-p. 604
9.2.2.C   Adjustment Ratio
9.2.2.Ca   Bundling Mode Indicator [R6]   PDF-p. 605
9.2.2.D   Cell Capability Container FDD [R5]
9.2.2.E   Cell Portion ID [R6]   PDF-p. 608
9.2.2.1   Chip Offset
9.2.2.2   Closed Loop Mode1 Support Indicator   PDF-p. 609
9.2.2.3   Closed Loop Mode2 Support Indicator
9.2.2.3A   Closed Loop Timing Adjustment Mode      Up
9.2.2.4   Compressed Mode Method
9.2.2.4A   DCH FDD Information
9.2.2.4B   E-DCH FDD Information [R6]   PDF-p. 610
9.2.2.4C   E-DCH FDD Information Response [R6]   PDF-p. 611
9.2.2.4D   E-DCH FDD DL Control Channel Information [R6]   PDF-p. 612
9.2.2.4E   E-DCH RL Indication [R6]   PDF-p. 614
9.2.2.4F   E-DCH FDD Information To Modify [R6]
9.2.2.4G   E-DCH Transport Format Combination Set Information (E-TFCS Information) [R6]   PDF-p. 618
9.2.2.4J   E-TTI [R6]   PDF-p. 620
9.2.2.4K   E-DPCCH Power Offset [R6]      Up
9.2.2.4KA   Void
9.2.2.4L   E-DCH HARQ Power Offset FDD [R6]
9.2.2.4M   Void
9.2.2.4MA   Void
9.2.2.4MB   Void
9.2.2.4MC   E-DCH MAC-d Flows Information [R6]
9.2.2.4MD   Void
9.2.2.4ME   Void
9.2.2.4MF   Void
9.2.2.4MG   E-DCH Maximum Bitrate [R6]   PDF-p. 622
9.2.2.4MH   Void
9.2.2.4MI   E-DCH Reference Power Offset [R6]
9.2.2.4MJ   Void
9.2.2.4N   Maximum Number of Bits per MAC-e PDU for Non-scheduled Transmission [R6]   PDF-p. 623
9.2.2.4O   HARQ Process Allocation For 2ms TTI [R6]
9.2.2.4P   Reference E-TFCI Power Offset [R6]
9.2.2.4Q   Extended Reference E-TFCI Power Offset [R7]
9.2.2.4R   Extended Maximum Number of Bits per MAC-e PDU for Non-scheduled Transmission [R7]   PDF-p. 624
9.2.2.4S   Transport Bearer Not Requested Indicator [R7]      Up
9.2.2.4T   Transport Bearer Not Setup Indicator [R7]
9.2.2.5   D-Field Length
9.2.2.6   Diversity Control Field
9.2.2.7   Diversity Indication
9.2.2.8   Diversity Mode
9.2.2.9   DL DPCH Slot Format   PDF-p. 625
9.2.2.9A   DL DPCH Timing Adjustment [R5]
9.2.2.10   DL Power
9.2.2.10A   DL Power Balancing Information [R5]
9.2.2.10B   DL Power Balancing Activation Indicator [R5]   PDF-p. 626      Up
9.2.2.10C   DL Reference Power Information [R5]
9.2.2.10D   DL Power Balancing Updated Indicator [R5]   PDF-p. 627
9.2.2.11   DL Scrambling Code
9.2.2.12   Downlink Frame Type
9.2.2.12A   DPC Mode [R4]
9.2.2.13   DRAC Control
9.2.2.13A   DSCH FDD Information   PDF-p. 628
9.2.2.13B   DSCH FDD Information Response
9.2.2.13Bb   DSCH-RNTI
9.2.2.13C   FDD DCHs To Modify      Up
9.2.2.13D   Enhanced DSCH PC [R4]
9.2.2.13E   Enhanced DSCH PC Counter [R4]
9.2.2.13F   Enhanced DSCH PC Indicator [R4]
9.2.2.13G   Enhanced DSCH PC Wnd [R4]
9.2.2.13H   Enhanced DSCH Power Offset [R4]   PDF-p. 629
9.2.2.13I   Enhanced Primary CPICH Ec/No [R5]
9.2.2.14   FDD DL Channelisation Code Number
9.2.2.14A   FDD DL Code Information
9.2.2.15   FDD S-CCPCH Offset
9.2.2.16   FDD TPC Downlink Step Size      Up
9.2.2.16A   First RLS Indicator   PDF-p. 630
9.2.2.17   Gap Position Mode
9.2.2.18   Gap Period (TGP)
9.2.2.19   Gap Starting Slot Number (SN)
9.2.2.19a   HS-DSCH FDD Information [R5]
9.2.2.19aa   HS-DSCH FDD Secondary Serving Information [R8]   PDF-p. 632
9.2.2.19b   HS-DSCH FDD Information Response [R5]   PDF-p. 634
9.2.2.19ba   HS-DSCH FDD Secondary Serving Information Response [R8]   PDF-p. 635
9.2.2.19bb   HS-DSCH FDD Secondary Serving Information To Modify [R8]   PDF-p. 636
9.2.2.19bc   HS-DSCH FDD Secondary Serving Information To Modify Unsynchronised [R8]   PDF-p. 638      Up
9.2.2.19c   HS-DSCH FDD Update Information [R5]   PDF-p. 640
9.2.2.19ca   HS-DSCH FDD Secondary Serving Update Information [R8]   PDF-p. 641
9.2.2.19xx   HS-DSCH Configured Indicator [R6]
9.2.2.19d   HS-SCCH Power Offset [R7]   PDF-p. 642
9.2.2.19e   E-DCH FDD Update Information [R6]
9.2.2.19f   HS-DSCH Serving Cell Change Information [R6]
9.2.2.19g   HS-DSCH Serving Cell Change Information Response [R6]   PDF-p. 643
9.2.2.19ga   HS-DSCH Secondary Serving Cell Change Information Response [R8]
9.2.2.19x   HS-DSCH TB Size Table Indicator [R7]
9.2.2.19h   E-DCH Serving Cell Change Information Response [R6]   PDF-p. 644      Up
9.2.2.20   IB_SG_POS
9.2.2.21   IB_SG_REP
9.2.2.21x   Inner Loop DL PC Status
9.2.2.21A   Limited Power Increase
9.2.2.21B   IPDL FDD Parameters   PDF-p. 645
9.2.2.21C   Length of TFCI2 [R4]
9.2.2.21D   Void
9.2.2.21E   Void
9.2.2.21F   Void
9.2.2.22   Max Adjustment Period
9.2.2.23   Max Adjustment Step
9.2.2.24   Max Number of UL DPDCHs
9.2.2.24a   CQI Feedback Cycle k [R5]   PDF-p. 646      Up
9.2.2.24b   CQI Power Offset [R5]
9.2.2.24c   CQI Repetition Factor [R5]
9.2.2.24d   Measurement Power Offset [R5]
9.2.2.24e   Maximum Set of E-DPDCHs [R6]
9.2.2.24f   Void
9.2.2.24x   eighbouringnisation Code Length [R10]   PDF-p. 647
9.2.2.25   Min UL Channelisation Code Length
9.2.2.26   Multiplexing Position
9.2.2.26x   NACK Power Offset [R5]
9.2.2.26A   Number of DL Channelisation Codes
9.2.2.27   Pattern Duration (PD)      Up
9.2.2.27x   PC Preamble   PDF-p. 648
9.2.2.27A   PDSCH Code Mapping
9.2.2.27B   Phase Reference Update Indicator [R5]
9.2.2.28   Power Adjustment Type
9.2.2.29   Power Control Mode (PCM)
9.2.2.30   Power Offset
9.2.2.31   Power Resume Mode (PRM)
9.2.2.31A   Preamble Signatures
9.2.2.32   Primary CPICH Ec/No   PDF-p. 649
9.2.2.32A   Primary CPICH Usage For Channel Estimation [R5]      Up
9.2.2.33   Propagation Delay (PD)
9.2.2.33x   Extended Propagation Delay [R7]
9.2.2.33A   PRACH Minimum Spreading Factor
9.2.2.34   QE-Selector
9.2.2.34x   Qth Parameter [R5]   PDF-p. 650
9.2.2.34A   RACH Sub Channel Numbers
9.2.2.35   RL Set ID
9.2.2.35x   RL Specific E-DCH Information [R6]
9.2.2.35A   Received Total Wide Band Power
9.2.2.36   S-Field Length      Up
9.2.2.36A   Void
9.2.2.37   Scrambling Code Change   PDF-p. 651
9.2.2.37A   Scrambling Code Number
9.2.2.37B   Secondary CCPCH Info
9.2.2.38   Secondary CCPCH Slot Format
9.2.2.38A   Secondary CPICH Information [R5]
9.2.2.38B   Secondary CPICH Information Change [R5]
9.2.2.38C   Serving E-DCH RL [R6]
9.2.2.39   Slot Number (SN)   PDF-p. 652
9.2.2.39x   Split Type
9.2.2.39A   SRB Delay      Up

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